Seminar Series Archive

High-performance workloads demand heterogeneous processing, tiered memory architecture, infrastructure accelerators such as SmartNICs, and infrastructure processing units to meet the demands of the emerging compute landscape. Applications such as artificial intelligence, machine learning, data analytics, 5G, automotive, and high-performance computing are driving significant changes within cloud computing, intelligent edge and client computing infrastructure. Interconnect is a key pillar in this evolving computational landscape. The recent advent of Compute Express Link (CXL), a new open standard for cache-coherent interconnect, with its memory and coherency semantics has made it possible to pool computational and memory resources at the rack level using low-latency, higher-throughput, and memory-coherent access mechanisms. CXL is adopting networking features such as multi-host connectivity, pooled memory, persistence flows, and fabric managers while keeping its low-latency load-store semantics intact. The load-store I/O interconnects such as PCI Express (PCIe) and CXL are evolving to provide efficient access mechanisms across multiple nodes with advanced atomics, acceleration, SmartNICs, persistent memory support, etc. In this talk we will explore how synergistic evolution across load-store interconnects and fabrics can benefit the compute infrastructure of the future.

Dr. Debendra Das Sharma is an Intel Senior Fellow and chief architect of the I/O Technology and Standards Group at the Data Platforms and AI Group, Intel Corporation. He drives PCI Express, Compute Express Link (CXL), Universal Chiplet Interconnect Express (UCIe), and Intel’s Coherency interconnect. He is a member of the Board of Directors of PCI-SIG and a lead contributor to PCIe specifications since its inception. He is a co-inventor and founding member of the CXL and UCIe consortia, Chair of UCIe Consortium, and co-leads the CXL Board Technical Task Force.
Dr. Das Sharma holds 160+ US patents and 400+ patents world-wide. He is a frequent keynote speaker, distinguished lecturer, invited speaker, and panelist at the IEEE Hot Interconnects, IEEE Cool Chips, IEEE 3DIC, Flash Memory Summit, SNIA SDC, PCI-SIG Developers Conference, CXL consortium events, Open Server Summit, Open Fabrics Alliance, and Intel Developer Forum. He has a B.Tech in Computer Science and Engineering from the Indian Institute of Technology, Kharagpur and a Ph.D. in Computer Engineering from the University of Massachusetts, Amherst.​ He has been awarded the IEEE CAS Industrial Pioneer Award in 2022, the Lifetime Contribution award by PCI-SIG, the IEEE Region 6 Outstanding Engineer Award, 2021, and Distinguished Alumnus Award from Indian Institute of Technology, Kharagpur, 2019.