All seminars will take place on Fridays at 11 a.m. in DBH 6011. Check seminar details below.
March 17, 2023
11:00am - 12:00pm
Towards High-Efficiency and High-Usability Hardware Acceleration
The exploding complexity and computation efficiency requirements of modern applications stimulate a strong demand for hardware acceleration with heterogeneous hardware acceleration platforms. The stringent requirements of these modern applications also pose several challenges for hardware acceleration systems. In particular, achieving high-efficiency, high-usability hardware acceleration targeting highly heterogeneous systems is one of the major challenges. In this talk, I will first give an overview of the challenges that modern hardware acceleration systems are facing, as well as my previous works in tackling these challenges. I will then introduce my recent representative works in detail, including PyLog language and compiler for Python-based high-level programming for FPGAs, Tangram language and compiler for highly efficient GPU code generation, Chai-FPGA for enabling CPU-FPGA collaborative computing, etc. Evaluation shows the promising performance and flexibility of these works when solving the hardware acceleration challenges. I will conclude the talk with my envision of future hardware acceleration research.
Sitao Huang is an assistant professor in the Department of Electrical Engineering and Computer Science at the University of California, Irvine. He received his Ph.D. degree and M.S. degree in Electrical and Computer Engineering from University of Illinois at Urbana-Champaign in 2021 and 2017 respectively. His research interests include hardware accelerators, compilers for accelerators, and heterogeneous systems. He is a 2022 DARPA Forward Riser. His research won the Best Paper Award at IDEAL 2021, Best Paper Nomination at ASP-DAC 2021, and the Student Innovation Award at the 2018 IEEE HPEC Graph Challenge.